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ltc2492 1 2492fb temperature (c) C55 C30 C 5 absolute error (c) 5 4 3 2 1 C4 C3 C2 C1 0 120 95 70 45 20 2492 ta01b C5 typical application features applications description 24-bit 2-/4-channel ? adc with easy drive input current cancellation the ltc ? 2492 is a 4-channel (2-channel differential), 24-bit, no latency ?? adc with easy drive? technology. the patented sampling scheme eliminates dynamic input current errors and the shortcomings of on-chip buffering through automatic cancellation of differential input current. this allows large external source impedances and rail-to- rail input signals to be directly digitized while maintaining exceptional dc accuracy. the ltc2492 includes a high accuracy temperature sensor and an integrated oscillator. this device can be con? gured to measure an external signal (from combinations of 4 analog input channels operating in single-ended or differential modes) or its internal temperature sensor. it can be programmed to reject line frequencies of 50hz, 60hz, or simultaneous 50hz/60hz and con? gured to double its output rate. the integrated temperature sensor offers 1/30th c resolution and 2c absolute accuracy. the ltc2492 allows a wide common mode input range (0v to v cc ), independent of the reference voltage. any combination of single-ended or differential inputs can be selected and the ? rst conversion after a new channel selection is valid. data acquisition system with temperature compensation , lt, ltc and ltm are registered trademarks of linear technology corporation. no latency ? and easy drive are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. up to 2 differential or 4 single-ended inputs easy drive technology enables rail-to-rail inputs with zero differential input current directly digitizes high impedance sensors with full accuracy 600nv rms noise integrated high accuracy temperature sensor gnd to v cc input/reference common mode range programmable 50hz, 60hz, or simultaneous 50hz/60hz rejection mode 2ppm inl, no missing codes 1ppm offset and 15ppm full-scale error 2x speed mode/reduced power mode (15hz using internal oscillator and 80a at 7.5hz output) no latency: digital filter settles in a single cycle, even after a new channel is selected single supply 2.7v to 5.5v operation (0.8mw) internal oscillator tiny dfn 4mm 3mm package direct sensor digitizer direct temperature measurement instrumentation industrial process control absolute temperature error sdi sck sdo cs f o ref + v cc 2.7v to 5.5v 10f com ref C 24-bit ? adc with easy-drive 4-channel mux temperature sensor in + in C 2492 ta01a 4-wire spi interface ch0 ch1 ch3 ch2 0.1f osc
ltc2492 2 2492fb electrical characteristics (normal speed) absolute maximum ratings supply voltage (v cc ) ...................................? 0.3v to 6v analog input voltage (ch0 to ch3, com) ................. ? 0.3v to (v cc + 0.3v) ref + , ref ? .................................. ? 0.3v to (v cc + 0.3v) digital input voltage ..................... ? 0.3v to (v cc + 0.3v) digital output voltage .................. ? 0.3v to (v cc + 0.3v) operating temperature range ltc2492c ................................................ 0c to 70c ltc2492i..............................................? 40c to 85c storage temperature range ...................? 65c to 150c (notes 1, 2) 1 2 3 4 5 6 7 14 13 12 11 10 9 8 ref ? ref + v cc ch3 ch2 ch1 ch0 f o sdi sck cs sdo gnd com de package 14-lead (4mm s 3mm) plastic dfn 15 t jmax = 125c, ja = 37c/w exposed pad (pin 15) is gnd, must be soldered to pcb the o denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (notes 3, 4) parameter conditions min typ max units resolution (no missing codes) 0.1v v ref v cc , ?fs v in +fs (note 5) 24 bits integral nonlinearity 5v v cc 5.5v, v ref = 5v, v in(cm) = 2.5v (note 6) 2.7v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v (note 6) o 2 1 10 ppm of v ref ppm of v ref offset error 2.5v v ref v cc , gnd in + = in ? v cc (note 14) o 0.5 2.5 v offset error drift 2.5v v ref v cc , gnd in + = in ? v cc 10 nv/c positive full-scale error 2.5v v ref v cc , in + = 0.75v ref , in ? = 0.25v ref o 25 ppm of v ref positive full-scale error drift 2.5v v ref v cc , in + = 0.75v ref , in ? = 0.25v ref 0.1 ppm of v ref /c negative full-scale error 2.5v v ref v cc , in + = 0.25v ref , in ? = 0.75v ref o 25 ppm of v ref negative full-scale error drift 2.5v v ref v cc , in + = 0.25v ref , in ? = 0.75v ref 0.1 ppm of v ref /c total unadjusted error 5v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v 5v v cc 5.5v, v ref = 5v, v in(cm) = 2.5v 2.7v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v 15 15 15 ppm of v ref ppm of v ref ppm of v ref output noise 5.5v < v cc < 2.7v, 2.5v v ref v cc , gnd in + = in ? v cc (note 13) 0.6 v rms internal ptat signal t a = 27c (note 14) 27.8 28.0 28.2 mv internal ptat temperature coef? cient 93.5 v/c lead free finish tape and reel part marking* package description temperature range ltc2492cde#pbf ltc2492cde#trpbf 2492 14-lead (4mm mm) lastic dfn 0c to 70c ltc242ide#bf ltc242ide#trbf 242 14-lead (4mm mm) lastic dfn C 40c to 85c consult ltc areting for parts speci ed with wider operating temperature ranges. *the temperature grade is identi ed by a label on the shipping container. consult ltc areting for information on non-standard lead based nish parts. for more information on lead free part maring, go to httpwww.linear.comleadfree for more information on tape and reel speci cations, go to httpwww.linear.comtapeandreel in configration order inforation
ltc2492 3 2492fb electrical characteristics (2x speed) the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (notes 3, 4) parameter conditions min typ max units resolution (no missing codes) 0.1v v ref v cc , Cfs v in +fs (note 5) 24 bits integral nonlinearity 5v v cc 5.5v, v ref = 5v, v in(cm) = 2.5v (note 6) 2.7v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.2v (note 6) 2 1 10 ppm of v ref ppm of v ref offset error 2.5v v ref v cc , gnd in + = in C v cc (note 14) 0.2 2 mv offset error drift 2.5v v ref v cc , gnd in + = in C v cc 100 nv/c positive full-scale error 2.5v v ref v cc , in + = 0.75v ref , in C = 0.25v ref 25 ppm of v ref positive full-scale error drift 2.5v v ref v cc , in + = 0.75v ref , in C = 0.25v ref 0.1 ppm of v ref /c negative full-scale error 2.5v v ref v cc , in + = 0.25v ref , in C = 0.75v ref 25 ppm of v ref negative full-scale error drift 2.5v v ref v cc , in + = 0.25v ref , in C = 0.75v ref 0.1 ppm of v ref /c output noise 5v v cc 2.5v, v ref = 5v, gnd in + = in C v cc 0.85 v rms converter characteristics the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) parameter conditions min typ max units input common mode rejection dc 2.5v v ref v cc , gnd in + = in C v cc (note 5) 140 db input common mode rejection 50hz 2% 2.5v v ref v cc , gnd in + = in C v cc (note 5) 140 db input common mode rejection 60hz 2% 2.5v v ref v cc , gnd in + = in C v cc (note 5) 140 db input normal mode rejection 50hz 2% 2.5v v ref v cc , gnd in + = in C v cc (notes 5, 7) 110 120 db input normal mode rejection 60hz 2% 2.5v v ref v cc , gnd in + = in C v cc (notes 5, 8) 110 120 db input normal mode rejection 50hz/60hz 2% 2.5v v ref v cc , gnd in + = in C v cc (notes 5, 9) 87 db reference common mode rejection dc 2.5v v ref v cc , gnd in + = in C v cc (note 5) 120 140 db power supply rejection dc v ref = 2.5v, in + = in C = gnd 120 db power supply rejection, 50hz 2% v ref = 2.5v, in + = in C = gnd (notes 7, 9) 120 db power supply rejection, 60hz 2% v ref = 2.5v, in + = in C = gnd (notes 8, 9) 120 db
ltc2492 4 2492fb digital inputs and digital outputs the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) analog input and reference the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) symbol parameter conditions min typ max units in + absolute/common mode in + voltage (in + corresponds to the selected positive input channel) gnd C 0.3v v cc + 0.3v v in C absolute/common mode in C voltage (in C corresponds to the selected negative input channel) gnd C 0.3v v cc + 0.3v v v in input differential voltage range (in + C in C ) Cfs +fs v fs full scale of the differential input (in + C in C ) 0.5v ref v lsb least signi? cant bit of the output code fs/2 24 ref + absolute/common mode ref + voltage 0.1 v cc v ref C absolute/common mode ref C voltage gnd ref + C 0.1v v v ref reference voltage range (ref + C ref C ) 0.1 v cc v cs(in + )in + sampling capacitance 11 pf cs(in C )in C sampling capacitance 11 pf cs(v ref )v ref sampling capacitance 11 pf i dc_leak(in + ) in + dc leakage current sleep mode, in + = gnd C10 1 10 na i dc_leak(in C ) in C dc leakage current sleep mode, in C = gnd C10 1 10 na i dc_leak(ref + ) ref + dc leakage current sleep mode, ref + = v cc C100 1 100 na i dc_leak(ref C ) ref C dc leakage current sleep mode, ref C = gnd C100 1 100 na t open mux break-before-make 50 ns qirr mux off isolation v in = 2v p-p dc to 1.8mhz 120 db symbol parameter conditions min typ max units v ih high level input voltage (`c`s, f o , sdi) 2.7v v cc 5.5v v cc C 0.5 v v il low level input voltage (`c`s, f o , sdi) 2.7v v cc 5.5v 0.5 v v ih high level input voltage (sck) 2.7v v cc 5.5v (notes 10, 15) v cc C 0.5 v v il low level input voltage (sck) 2.7v v cc 5.5v (notes 10, 15) 0.5 v i in digital input current (`c`s, f o , sdi) 0v v in v cc C10 10 a i in digital input current (sck) 0v v in v cc (notes 10, 15) C10 10 a c in digital input capacitance (`c`s, f o , sdi) 10 pf c in digital input capacitance (sck) (notes 10, 15) 10 pf v oh high level output voltage (sdo) i o = C 800a v cc C 0.5 v v ol low level output voltage (sdo) i o = 1.6ma 0.4 v v oh high level output voltage (sck) i o = C 800a (notes 10, 17) v cc C 0.5 v v ol low level output voltage (sck) i o = 1.6ma (notes 10, 17) 0.4 v i oz hi-z output leakage (sdo) C10 10 a power requirements the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) symbol parameter conditions min typ max units v cc supply voltage 2.7 5.5 v i cc supply current conversion current (note 12) temperature measurement (note 12) sleep mode (note 12) 160 200 1 275 300 2 a a a
ltc2492 5 2492fb symbol parameter conditions min typ max units f eosc external oscillator frequency range (note 16) 10 4000 khz t heo external oscillator high period 0.125 100 s t leo external oscillator low period 0.125 100 s t conv_1 conversion time for 1x speed mode 50hz mode 60hz mode simultaneous 50/60hz mode external oscillator 157.2 131 144.1 160.3 133.6 146.9 41036/f eosc (in khz) 163.5 136.3 149.9 ms ms ms ms t conv_2 conversion time for 2x speed mode 50hz mode 60hz mode simultaneous 50/60hz mode external oscillator 78.7 65.6 72.2 80.3 66.9 73.6 20556/f eosc (in khz) 81.9 68.2 75.1 ms ms ms ms f isck internal sck frequency internal oscillator (notes 10, 17) external oscillator (notes 10, 11, 15) 38.4 f eosc /8 khz khz d isck internal sck duty cycle (notes 10, 17) 45 55 % f esck external sck frequency range (notes 10, 11, 15) 4000 khz t lesck external sck low period (notes 10, 11, 15) 125 ns t hesck external sck high period (notes 10, 11, 15) 125 ns t dout_isck internal sck 32-bit data output time internal oscillator (notes 10, 17) external oscillator (notes 10, 11, 15) 0.81 0.83 256/f eosc (in khz) 0.85 ms ms t dout_esck external sck 32-bit data output time (notes 10, 11, 15) 32/f esck (in khz) ms t 1 cs to sdo low 0 200 ns t 2 cs to sdo hi-z 0 200 ns t 3 cs to sck internal sck mode 0 200 ns t 4 cs to sck external sck mode 50 ns t kqmax sck to sdo valid 200 ns t kqmin sdo hold after sck (note 5) 15 ns t 5 sck set-up before cs 50 ns t 7 sdi setup before sck (note 5) 100 ns t 8 sdi hold after sck (note 5) 100 ns digital inputs and digital outputs the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd. note 3: unless otherwise speci? ed: v cc = 2.7v to 5.5v v refcm = v ref /2, f s = 0.5v ref v in = in + C in C , v in(cm) = (in + C in C )/2, where in + and in C are the selected input channels. note 4: use internal conversion clock or external conversion clock source with f eosc = 307.2khz unless other wise speci? ed. note 5: guaranteed by design, not subject to test. note 6: integral nonlinearity is de? ned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: 50hz mode (internal oscillator) or f eosc = 256khz 2% (external oscillator). note 8: 60hz mode (internal oscillator) or f eosc = 307.2khz 2% (external oscillator). note 9: simultaneous 50hz/60hz mode (internal oscillator) or f eosc = 280khz 2% (external oscillator). note 10: the sck can be con? gured in external sck mode or internal sck mode. in external sck mode, the sck pin is used as a digital input and the driving clock is f esck . in the internal sck mode, the sck pin is used as a digital output and the output clock signal during the data output is f isck . note 11: the external oscillator is connected to the f o pin. the external oscillator frequency, f eosc , is expressed in khz. note 12: the converter uses its internal oscillator. note 13: the output noise includes the contribution of the internal calibration operations. note 14: guaranteed by design and test correlation. note 15: the converter is in external sck mode of operation such that the sck pin is used as a digital input. the frequency of the clock signal driving sck during the data output is f esck and is expressed in hz. note 16: refer to applications information section for performance vs data rate graphs. note 17: the converter in internal sck mode of operation such that the sck pin is used as a digital output.
ltc2492 6 2492fb output reading (v) C3 number of readings (%) 8 10 12 0.6 2492 g07 6 4 C1.8 C0.6 C2.4 1.2 C1.2 0 1.8 2 0 14 10,000 consecutive readings v cc = 5v v ref = 5v v in = 0v t a = 25c rms = 0.60v average = C0.69v output reading (v) C3 number of readings (%) 8 10 12 0.6 2492 g08 6 4 C1.8 C0.6 C2.4 1.2 C1.2 0 1.8 2 0 14 10,000 consecutive readings v cc = 2.7v v ref = 2.5v v in = 0v t a = 25c rms = 0.59v average = C0.19v time (hours) 0 C5 adc reading (v) C3 C1 1 10 20 30 40 2492 g09 50 3 5 C4 C2 0 2 4 60 v cc = 5v, v ref = 5v, v in = 0v, v in(cm) = 2.5v t a = 25c, rms noise = 0.60v input voltage (v) C3 inl (ppm of v ref ) C1 1 3 C2 0 2 C1.5 C 0.5 0.5 1.5 2492 g01 2.5 C2 C2.5 C1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v f o = gnd 85c C45c 25c input voltage (v) C3 inl (ppm of v ref ) C1 1 3 C2 0 2 C 0.75 C 0.25 0.25 0.75 2492 g02 1.25 C1.25 v cc = 5v v ref = 2.5v v in(cm) = 1.25v f o = gnd C 45c, 25c, 90c input voltage (v) C3 inl (ppm of v ref ) C1 1 3 C2 0 2 C0.75 C0.25 0.25 0.75 2492 g03 1.25 C1.25 v cc = 2.7v v ref = 2.5v v in(cm) = 1.25v f o = gnd C45c, 25c, 90c input voltage (v) C12 tue (ppm of v ref ) C4 4 12 C8 0 8 C1.5 C0.5 0.5 1.5 2492 g04 2.5 C2 C2.5 C1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v f o = gnd 85c 25c C45c input voltage (v) C12 tue (ppm of v ref ) C4 4 12 C8 0 8 C0.75 C0.25 0.25 0.75 2492 g05 1.25 C1.25 v cc = 5v v ref = 2.5v v in(cm) = 1.25v f o = gnd 85c 25c C45c input voltage (v) C12 tue (ppm of v ref ) C4 4 12 C8 0 8 C0.75 C0.25 0.25 0.75 2492 g06 1.25 C1.25 v cc = 2.7v v ref = 2.5v v in(cm) = 1.25v f o = gnd 85c 25c C45c typical performance characteristics integral nonlinearity (v cc = 5v, v ref = 5v) integral nonlinearity (v cc = 5v, v ref = 2.5v) integral nonlinearity (v cc = 2.7v, v ref = 2.5v) total unadjusted error (v cc = 5v, v ref = 5v) total unadjusted error (v cc = 5v, v ref = 2.5v) total unadjusted error (v cc = 2.7v, v ref = 2.5v) noise histogram (6.8sps) noise histogram (7.5sps) long-term adc readings
ltc2492 7 2492fb input differential voltage (v) 0.4 rms noise (v) 0.6 0.8 1.0 0.5 0.7 0.9 C1.5 C0.5 0.5 1.5 2492 g10 2.5 C2 C2.5 C1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v t a = 25c v in(cm) (v) C1 rms noise (v) 0.8 0.9 1.0 24 2492 g11 0.7 0.6 01 356 0.5 0.4 v cc = 5v v ref = 5v v in = 0v t a = 25c temperature (c) C45 0.4 rms noise (v) 0.5 0.6 0.7 0.8 1.0 C30 C15 15 0 304560 2492 g12 75 90 0.9 v cc = 5v v ref = 5v v in = 0v v in(cm) = gnd v ref (v) 0 0.4 rms noise (v) 0.5 0.6 0.7 0.8 0.9 1.0 1234 2492 g14 5 v cc = 5v v in = 0v v in(cm) = gnd t a = 25c v in(cm) (v) C1 offset error (ppm of v ref ) 0.1 0.2 0.3 24 2492 g15 0 C0.1 01 356 C0.2 C0.3 v cc = 5v v ref = 5v v in = 0v t a = 25c v cc (v) 2.7 rms noise (v) 0.8 0.9 1.0 3.9 4.7 2492 g13 0.7 0.6 3.1 3.5 4.3 5.1 5.5 0.5 0.4 v ref = 2.5v v in = 0v v in(cm) = gnd t a = 25c temperature (c) C45 C0.3 offset error (ppm of v ref ) C0.2 0 0.1 0.2 C15 15 30 90 2492 g16 C0.1 C30 0 45 60 75 0.3 v cc = 5v v ref = 5v v in = 0v v in(cm) = gnd f o = gnd v cc (v) 2.7 offset error (ppm of v ref ) 0.1 0.2 0.3 3.9 4.7 2492 g17 0 C0.1 3.1 3.5 4.3 5.1 5.5 C0.2 C0.3 ref + = 2.5v ref C = gnd v in = 0v v in(cm) = gnd t a = 25c v ref (v) 0 C0.3 offset error (ppm of v ref ) C0.2 C0.1 0 0.1 0.2 0.3 1234 2492 g18 5 v cc = 5v ref C = gnd v in = 0v v in(cm) = gnd t a = 25c typical performance characteristics rms noise vs input differential voltage rms noise vs v in(cm) rms noise vs temperature (t a ) rms noise vs v cc rms noise vs v ref offset error vs v in(cm) offset error vs temperature offset error vs v cc offset error vs v ref
ltc2492 8 2492fb input voltage (v) C3 inl (ppm of v ref ) C1 1 3 C2 0 2 C1.5 C0.5 0.5 1.5 2492 g27 2.5 C2 C2.5 C1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v f o = gnd 25c, 90c C 45c temperature ( c) C45 100 conversion current ( a) 120 160 180 200 C15 15 30 90 2492 g24 140 C30 0 45 60 75 v cc = 5v v cc = 2.7v f o = gnd cs = gnd sck = nc sdo = nc sdi = gnd frequency at v cc (hz) 0 C140 rejection (db) C120 C80 C60 C40 0 20 100 140 2492 g22 C100 C20 80 180 220 200 40 60 120 160 v cc = 4.1v dc 1.4v v ref = 2.5v in + = gnd in C = gnd f o = gnd t a = 25c frequency at v cc (hz) 30600 C60 C40 0 30750 2492 g23 C80 C100 30650 30700 30800 C120 C140 C20 rejection (db) v cc = 4.1v dc 0.7v v ref = 2.5v in + = gnd in C = gnd f o = gnd t a = 25c temperature (c) C45 0 sleep mode current (a) 0.2 0.6 0.8 1.0 2.0 1.4 C15 15 30 90 2492 g25 0.4 1.6 1.8 1.2 C30 0 45 60 75 v cc = 5v v cc = 2.7v f o = gnd cs = v cc sck = nc sdo = nc sdi = gnd output data rate (readings/sec) 0 supply current (a) 500 450 400 350 300 250 200 150 100 80 2492 g26 20 40 60 100 70 10 30 50 90 v cc = 5v v cc = 3v v ref = v cc in + = gnd in C = gnd sck = nc sdo = nc sdi = gnd cs gnd f o = ext osc t a = 25c frequency at v cc (hz) 1 0 C20 C40 C60 C80 C100 C120 C140 1k 100k 2492 g21 10 100 10k 1m rejection (db) v cc = 4.1v dc v ref = 2.5v in + = gnd in C = gnd f o = gnd t a = 25c temperature (c) C45 C30 300 frequency (khz) 304 310 C15 30 45 2492 g19 302 308 306 15 0 60 75 90 v cc = 4.1v v ref = 2.5v v in = 0v v in(cm) = gnd f o = gnd v cc (v) 2.5 300 frequency (khz) 302 304 306 308 310 3.0 3.5 4.0 4.5 2492 g20 5.0 5.5 v ref = 2.5v v in = 0v v in(cm) = gnd f o = gnd t a = 25c typical performance characteristics on-chip oscillator frequency vs temperature on-chip oscillator frequency vs v cc psrr vs frequency at v cc psrr vs frequency at v cc psrr vs frequency at v cc conversion current vs temperature sleep mode current vs temperature conversion current vs output data rate integral nonlinearity (2x speed mode; v cc = 5v, v ref = 5v)
ltc2492 9 2492fb temperature (c) C45 offset error (v) 200 210 220 75 2492 g33 190 180 160 C15 15 45 C30 90 0 30 60 170 240 230 v cc = 5v v ref = 5v v in = 0v v in(cm) = gnd f o = gnd v in(cm) (v) C1 180 offset error (v) 182 186 188 190 200 194 1 3 4 2492 g32 184 196 198 192 0 2 5 6 v cc = 5v v ref = 5v v in = 0v f o = gnd t a = 25c v ref (v) 0 rms noise (v) 0.6 0.8 1.0 4 2492 g31 0.4 0.2 0 1 2 3 5 v cc = 5v v in = 0v v in(cm) = gnd f o = gnd t a = 25c output reading (v) 179 number of readings (%) 8 10 12 186.2 2492 g30 6 4 181.4 183.8 188.6 2 0 16 14 10,000 consecutive readings v cc = 5v v ref = 5v v in = 0v t a = 25c rms = 0.85v average = 0.184mv input voltage (v) C3 inl (ppm of v ref ) C1 1 3 C2 0 2 C0.75 C0.25 0.25 0.75 2492 g29 1.25 C1.25 v cc = 2.7v v ref = 2.5v v in(cm) = 1.25v f o = gnd 90c C45c, 25c input voltage (v) C3 inl (ppm of v ref ) C1 1 3 C2 0 2 C0.75 C0.25 0.25 0.75 2492 g28 1.25 C1.25 v cc = 5v v ref = 2.5v v in(cm) = 1.25v f o = gnd 90c C45c, 25c typical performance characteristics integral nonlinearity (2x speed mode; v cc = 5v, v ref = 2.5v) integral nonlinearity (2x speed mode; v cc = 2.7v, v ref = 2.5v) noise histogram (2x speed mode) rms noise vs v ref (2x speed mode) offset error vs v in(cm) (2x speed mode) offset error vs temperature (2x speed mode)
ltc2492 10 2492fb frequency at v cc (hz) 30600 C60 C40 0 30750 2492 g38 C80 C100 30650 30700 30800 C120 C140 C20 rejection (db) v cc = 4.1v dc 0.7v ref + = 2.5v ref C = gnd in + = gnd in C = gnd f o = gnd t a = 25c frequency at v cc (hz) 1 0 C20 C40 C60 C80 C100 C120 C140 1k 100k 2492 g36 10 100 10k 1m rejection (db) v cc = 4.1v dc ref + = 2.5v ref C = gnd in + = gnd in C = gnd f o = gnd t a = 25c v ref (v) 0 offset error (v) 190 200 210 3 5 2492 g35 180 170 160 12 4 220 230 240 v cc = 5v v in = 0v v in(cm) = gnd f o = gnd t a = 25c v cc (v) 2 2.5 0 offset error (v) 100 250 3 4 4.5 2492 g34 50 200 150 3.5 5 5.5 v ref = 2.5v v in = 0v v in(cm) = gnd f o = gnd t a = 25c frequency at v cc (hz) 0 C140 rrejection (db) C120 C80 C60 C40 0 20 100 140 2492 g37 C100 C20 80 180 220 200 40 60 120 160 v cc = 4.1v dc 1.4v ref + = 2.5v ref C = gnd in + = gnd in C = gnd f o = gnd t a = 25c typical performance characteristics offset error vs v cc (2x speed mode) offset error vs v ref (2x speed mode) psrr vs frequency at v cc (2x speed mode) psrr vs frequency at v cc (2x speed mode) psrr vs frequency at v cc (2x speed mode)
ltc2492 11 2492fb pin functions f o (pin 1): frequency control pin. digital input that controls the internal conversion clock rate. when f o is connected to gnd, the converter uses its internal oscillator running at 307.2khz. the conversion clock may also be overridden by driving the f o pin with an external clock in order to change the output rate and the digital ? lter rejection null. sdi (pin 2): serial data input. this pin is used to select the line frequency rejection mode, 1 or 2 speed mode, temperature sensor, as well as the input channel. the serial data input is applied under control of the serial clock (sck) during the data output/input operation. the ? rst conversion following a new input or mode change is valid. sck (pin 3): bidirectional, digital i/o, clock pin. in internal serial clock operation mode, sck is generated internally and is seen as an output on the sck pin. in external serial clock operation mode, the digital i/o clock is externally applied to the sck pin. the serial clock operation mode is determined by the logic level applied to the sck pin at power up and during the most recent falling edge of cs cs (pin 4): active low chip select. a low on this pin enables the digital input/output and wakes up the adc. following each conversion, the adc automatically enters the sleep mode and remains in this low power state as long as cs is high. a low-to-high transition on cs during the data output aborts the data transfer and starts a new conversion. sdo (pin 5): three-state digital output. during the data output period, this pin is used as the serial data output. when the chip select pin is high, the sdo pin is in a high impedance state. during the conversion and sleep periods, this pin is used as the conversion status output. when the conversion is in progress this pin is high; once the conversion is complete sdo goes low. the conversion status is monitored by pulling cs low. gnd (pin 6): ground. connect this pin to a common ground plane through a low impedance connection. com (pin 7): the common negative input (in C ) for all single-ended multiplexer con? gurations. the voltage on ch0 to ch3 and com pins can have any value between gnd C 0.3v to v cc + 0.3v. within these limits, the two selected inputs (in + and in C ) provide a bipolar input range (v in = in + C in C ) from C0.5 ? v ref to 0.5 ? v ref . outside this input range, the converter produces unique over-range and under-range output codes. ch0 to ch3 (pins 8-11): analog inputs. may be programmed for single-ended or differential mode. v cc (pin 12): positive supply voltage. bypass to gnd with a 10f tantalum capacitor in parallel with a 0.1f ceramic capacitor as close to the part as possible. ref + (pin 13), ref C (pin 14): differential reference input. the voltage on these pins can have any value between gnd and v cc as long as the reference positive input, ref + , remains more positive than the negative reference input, ref C , by at least 0.1v. the differential voltage (v ref = ref + C ref C ) sets the fullscale range for all input channels. when performing an on-chip temperature measurement, the minimum value of ref = 2v. exposed pad (pin 15): ground. this pin is ground and must be soldered to the pcb ground plane. for prototyping purposes, this pin may remain ? oating.
ltc2492 12 2492fb functional block diagram test circuits autocalibration and control differential 3rd order ? modulator decimating fir address internal oscillator serial interface gnd v cc ch0 ch1 ch2 ch3 com mux in + in C sdo sck ref + ref C cs sdi f o (int/ext) 2492 bd + C temp sensor 1.69k sdo 2492 tc01 hi-z to v oh v ol to v oh v oh to hi-z c load = 20pf 1.69k sdo 2492 tc02 hi-z to v ol v oh to v ol v ol to hi-z c load = 20pf v cc figure 1. functional block diagram
ltc2492 13 2492fb timing diagrams cs sdo sck sdi t 1 t 3 t 7 t 8 sleep t kqmax conversion data in/out t kqmin t 2 2492 td01 hi-z hi-z cs sdo sck sdi t 1 t 5 t 4 t 7 t 8 sleep t kqmax conversion data in/out t kqmin t 2 2492 td02 hi-z hi-z timing diagram using internal sck (sck high with cs ) timing diagram using external sck (sck low with cs )
ltc2492 14 2492fb applications information converter operation converter operation cycle the ltc2492 is a multi-channel, low power, delta- sigma analog-to-digital converter with an easy to use 4-wire interface and automatic differential input current cancellation. its operation is made up of four states (see figure 2). the converter operating cycle begins with the conversion, followed by the sleep state and ends with the data input/output cycle. the 4-wire interface consists of serial data output (sdo), serial clock (sck), chip select ( cs and serial data input (sdi).the interface, timing, operation cycle, and data output format is compatible with linears entire family of spi converters. initially, at power up, the ltc2492 performs a conversion. once the conversion is complete, the device enters the sleep state. while in this sleep state, if cs is high, power consumption is reduced by two orders of magnitude. the part remains in the sleep state as long as cs is high. the conversion result is held inde? nitely in a static shift register while the part is in the sleep state. once cs is pulled low, the device powers up, exits the sleep state, and enters the data input/output state. if cs is brought high before the ? rst rising edge of sck, the device returns to the sleep state and the power is reduced. if cs is brought high after the ? rst rising edge of sck, the data output cycle is aborted and a new conversion cycle begins. the data output corresponds to the conversion just completed. this result is shifted out on the serial data output pin (sdo) under the control of the serial clock pin (sck). data is updated on the falling edge of sck allowing the user to reliably latch data on the rising edge of sck (see figure 3). the con? guration data for the next conversion is also loaded into the device at this time. data is loaded from the serial data input pin (sdi) on each rising edge of sck. the data input/output cycle concludes once 32 bits are read out of the adc or when cs is brought high. the device automatically initiates a new conversion and the cycle repeats. through timing control of the cs and sck pins, the ltc2492 offers several ? exible modes of operation (internal or external sck and free-running conversion modes). these various modes do not require programming and do not disturb the cyclic operation described above. these modes of operation are described in detail in the serial interface timing modes section. ease of use the ltc2492 data output has no latency, ? lter settling delay, or redundant data associated with the conversion cycle. there is a one-to-one correspondence between the conversion and the output data. therefore, multiplexing multiple analog inputs is straight forward. each conversion, immediately following a newly selected input or mode, is valid and accurate to the full speci? cations of the device. the ltc2492 automatically performs offset and full scale calibration every conversion cycle independent of the input channel selected. this calibration is transparent to the user and has no effect with the operation cycle described above. the advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage variation, input channel, and temperature drift. figure 2. ltc2492 state transition diagram convert sleep channel select configuration select data output power up in + = ch0, in C = ch1 50/60hz,1x 2492 f02 cs = low and sck
ltc2492 15 2492fb applications information easy drive input current cancellation the ltc2492 combines a high precision delta-sigma adc with an automatic, differential, input current cancellation front end. a proprietary front end passive sampling network transparently removes the differential input current. this enables external rc networks and high impedance sensors to directly interface to the ltc2492 without external ampli? ers. the remaining common mode input current is eliminated by either balancing the differential input impedances or setting the common mode input equal to the common mode reference (see automatic differential input current cancellation section). this unique architecture does not require on-chip buffers, thereby enabling signals to swing beyond ground and v cc . moreover, the cancellation does not interfere with the transparent offset and full-scale auto-calibration and the absolute accuracy (full scale + offset + linearity + drift) is maintained even with external rc networks. power-up sequence the ltc2492 automatically enters an internal reset state when the power supply voltage v cc drops below approximately 2v. this feature guarantees the integrity of the conversion result, input channel selection, and serial clock mode. when v cc rises above this threshold, the converter creates an internal power-on-reset (por) signal with a duration of approximately 4ms. the por signal clears all internal registers. the conversion immediately following a por cycle is performed on the input channel in + = ch0, in C = ch1, simultaneous 50hz/60hz rejection and 1 output rate. the ? rst conversion following a por cycle is accurate within the speci? cation of the device if the power supply voltage is restored to (2.7v to 5.5v) before the end of the por interval. a new input channel, rejection mode, speed mode, or temperature selection can be programmed into the device during this ? rst data input/output cycle. reference voltage range this converter accepts a truly differential external reference voltage. the absolute/common mode voltage range for ref + and ref C pins covers the entire operating range of the device (gnd to v cc ). for correct converter operation, v ref must be positive (ref + > ref C ). the ltc2492 differential reference input range is 0.1v to v cc . for the simplest operation, ref + can be shorted to v cc and ref C can be shorted to gnd. the converter output noise is determined by the thermal noise of the front end circuits, and as such, its value in nanovolts is nearly constant with reference voltage. a decrease in reference voltage will not signi? cantly improve the converters effective resolution. on the other hand, a decreased reference will improve the converters overall inl performance. input voltage range the analog inputs are truly differential with an absolute, common mode range for the ch0 to ch3 and com input pins extending from gnd C 0.3v to v cc + 0.3v. outside these limits, the esd protection devices begin to turn on and the errors due to input leakage current increase rapidly. within these limits, the ltc2492 converts the bipolar differential input signal v in = in + C in C (where in + and in C are the selected input channels), from Cfs = C0.5 ? v ref to +fs = 0.5 ? v ref where v ref = ref + C ref C . outside this range, the converter indicates the overrange or the underrange condition using distinct output codes (see table 1). signals applied to the input (ch0 to ch3, com) may extend 300mv below ground and above v cc . in order to limit any fault current, resistors of up to 5k may be added in series with the input. the effect of series resistance on the converter accuracy can be evaluated from the curves presented in the input current/reference current sections. in addition, series resistors will introduce a temperature dependent error due to input leakage current. a 1na input leakage current will develop a 1ppm offset error on a 5k resistor if v ref = 5v. this error has a very strong temperature dependency.
ltc2492 16 2492fb applications information serial interface pins the ltc2492 transmits the conversion result, reads the input con? guration, and receives a start of conversion command through a synchronous 3- or 4-wire interface. during the conversion and sleep states, this interface can be used to access the converter status. during the data output state, it is used to read the conversion result, program the input channel, rejection frequency, speed multiplier, and select the temperature sensor. serial clock input/output (sck) the serial clock pin (sck) is used to synchronize the data input/output transfer. each bit is shifted out of the sdo pin on the falling edge of sck and data is shifted into the sdi pin on the rising edge of sck. the serial clock pin (sck) can be con? gured as either a master (sck is an output generated internally) or a slave (sck is an input and applied externally). master mode (internal sck) is selected by simply ? oating the sck pin. slave mode (external sck) is selected by driving sck low during power up and each falling edge of cs . speci? c details of these sck modes are described in the serial interface timing modes section. serial data output (sdo) the serial data output pin (sdo) provides the result of the last conversion as a serial bit stream (msb ? rst) during the data output state. in addition, the sdo pin is used as an end of conversion indicator during the conversion and sleep states. when cs is high, the sdo driver is switched to a high impedance state in order to share the data output line with other devices. if cs is brought low during the conversion phase, the eoc bit (sdo pin) will be driven high. once the conversion is complete, if cs is brought low, eoc will be driven low indicating the conversion is complete and the result is ready to be shifted out of the device. chip select ( cs ) the active low cs pin is used to test the conversion status, enable i/o data transfer, initiate a new conversion, control the duration of the sleep state, and set the sck mode. at the conclusion of a conversion cycle, while cs is high, the device remains in a low power sleep state where the supply current is reduced several orders of magnitude. in order to exit the sleep state and enter the data output state, cs must be pulled low. data is now shifted out the sdo pin under control of the sck pin as described previously. a new conversion cycle is initiated either at the conclusion of the data output cycle (all 32 data bits read) or by pulling cs high any time between the ? rst and 32nd rising edges of the serial clock (sck). in this case, the data output is aborted and a new conversion begins. serial data input (sdi) the serial data input (sdi) is used to select the input channel, rejection frequency, speed multiplier and to access the integrated temperature sensor. data is shifted into the device during the data output/input state on the rising edge of sck while cs is low. output data format the ltc2492 serial output stream is 32 bits long. the ? rst bit indicates the conversion status, the second bit is always zero, and the third bit conveys sign information. the next 24 bits are the conversion result, msb ? rst. the remaining 5 bits are sub lsbs beyond the 24-bit level that may be included in averaging or discarded without loss of resolution. bit 31 (? rst output bit) is the end of conversion ( eoc indicator. this bit is available on the sdo pin during the conversion and sleep states whenever cs is low. this bit is high during the conversion cycle, goes low once the conversion is complete, and is hi-z when cs is high. bit 30 (second output bit) is a dummy bit (dmy) and is always low. bit 29 (third output bit) is the conversion result sign indicator (sig). if the selected input (v in = in + C in C ) is greater than 0v, this bit is high. if v in < 0, this bit is low.
ltc2492 17 2492fb applications information bit 28 (fourth output bit) is the most signi? cant bit (msb) of the result. this bit in conjunction with bit 29 also provides underrange and overrange indication. if both bit 29 and bit 28 are high, the differential input voltage is above +fs. if both bit 29 and bit 28 are low, the differential input voltage is below Cfs. the function of these bits is summarized in table 1. table 1. ltc2492 status bits input range bit 31 eoc bit 30 dmy bit 29 sig bit 28 msb v in 0.5 ? v ref 0011 0v v in 0.5 ? v ref 0010 C0.5 ? v ref v in 0v 0001 v in C0.5 ? v ref 0000 bits 28 to 5 are the 24-bit conversion result msb ? rst. bit 5 is the least signi? cant bit (lsb 24 ). bits 4 to 0 are sub lsbs below the 24-bit level. bits 4 to 0 may be included in averaging or discarded without loss of resolution. data is shifted out of the sdo pin under control of the serial clock (sck) (see figure 3). whenever cs is high, sdo remains high impedance and sck is ignored. in order to shift the conversion result out of the device, cs must ? rst be driven low. eoc is seen at the sdo pin of the device once cs is pulled low. eoc changes in real time as a function of the internal oscillator or the clock applied to the f o pin from high to low at the completion of a conversion. this signal may be used as an interrupt for an external microcontroller. bit 31 ( eoc can be captured on the ? rst rising edge of sck. bit 30 is shifted out of the device on the ? rst falling edge of sck. the ? nal data bit (bit 0) is shifted out on the on the falling edge of the 31st sck and may be latched on the rising edge of the 32nd sck pulse. on the falling edge of the 32nd sck pulse, sdo goes high indicating the initiation of a new conversion cycle. this bit serves as eoc (bit 31) for the next conversion cycle. table 2 summarizes the output data format. as long as the voltage on the in + and in C pins remains between C0.3v and v cc + 0.3v (absolute maximum operating range) a conversion result is generated for any differential input voltage v in from Cfs = C0.5 ? v ref to +fs = 0.5 ? v ref . for differential input voltages greater than +fs, the conversion result is clamped to the value corresponding to +fs + 1lsb. for differential input voltages below Cfs, the conversion result is clamped to the value Cfs C 1lsb. input data format the ltc2492 serial input word is 13 bits long and contains two distinct sets of data. the ? rst set (sgl, odd, a2, a1, a0) is used to select the input channel. the second set of data (im, fa, fb, spd) is used to select the frequency rejection, speed mode (1 , 2 ), and temperature measurement. after power up, the device initiates an internal reset cycle which sets the input channel to ch0 to ch1 (in + = ch0, in C = ch1), the frequency rejection to simultaneous 50hz/60hz, and 1 output rate (auto-calibration enabled). the ? rst eoc cs sck (external) sdi sdo 2492 f03 conversion sleep data input/output msb bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 sig bit 29 0 bit 30 bit 31 1 0 en sgl a2 a1 a0 en2 im fa fb spd odd bit 18 bit 17 bit 0 1234567891011121314 32 don't care don't care figure 3. channel selection, con? guration selection and data output timing
ltc2492 18 2492fb applications information conversion automatically begins at power up using this default con? guration. once the conversion is complete, a new word may be written into the device. the ? rst three bits shifted into the device consist of two preamble bits and an enable bit. these bits are used to enable the device con? guration and input channel selection. valid settings for these three bits are 000, 100 and 101. other combinations should be avoided. if the ? rst three bits are 000 or 100, the following data is ignored (dont care) and the previously selected input channel and con? guration remain valid for the next conversion. if the ? rst three bits shifted into the device are 101, then the next ? ve bits select the input channel for the next conversion cycle (see table 3). the ? rst input bit (sgl) following the 101 sequence determines if the input selection is differential (sgl = 0) or single-ended (sgl = 1). for sgl = 0, two adjacent channels can be selected to form a differential input. for sgl = 1, one of four channels is selected as the positive input. the negative input is com for all single-ended operations. the remaining four bits (odd, a2, a1, a0) determine which channel(s) is/are selected and the polarity (for a differential input). the next serial input bit immediately following the input channel selection is the enable bit for the conversion con? guration (en2). if this bit is set to 0, then the next conversion is performed using the previously selected converter con? guration. a new con? guration can be loaded into the device by setting en2 = 1 (see table 4). the ? rst bit (im) is used to select the internal temperature sensor. if im = 1, the following conversion will be performed on the internal temperature sensor rather than the selected input channel. the next two bits (fa and fb) are used to set the rejection frequency. the ? nal bit (spd) is used to select either the 1x output rate if spd = 0 (auto-calibration is enabled and the offset is continuously calibrated and removed from the ? nal conversion result) or the 2x output rate if spd = 1 (offset calibration disabled, multiplexing output rates up to 15hz with no latency). when im = 1 (temperature measurement) spd will be ignored and the device will operate in 1 mode. the con? guration remains valid until table 3 channel selection mux address channel selection sgl odd/ sign a2 a1 a0 0 1 2 3 com *00000in + in C 00001 in + in C 01000in C in + 01001 in C in + 10000in + in C 10001 in + in C 11000 in + in C 11001 in + in C *default at power up table 2. output data format differential input voltage v in * bit 31 ` e ` o ` c bit 30 dmy bit 29 sig bit 28 msb bit 27 bit 26 bit 25 bit 5 lsb bits 4 to 0 sub lsbs v in * 0.5 ? v ref ** 0 0 1 1 0 0 0 0 00000 0.5 ? v ref ** C 1lsb 0 0 1 0 1 1 1 1 xxxxx 0.25 ? v ref ** 0 0 1 0 1 0 0 0 xxxxx 0.25 ? v ref ** C 1lsb 0 0 1 0 0 1 1 1 xxxxx 0 0 0 1 0 0 0 0 0 xxxxx C1lsb 0 0 0 1 1 1 1 1 xxxxx C0.25 ? v ref ** 0 0 0 1 1 0 0 0 xxxxx C0.25 ? v ref ** C 1lsb 0 0 0 1 0 1 1 1 xxxxx C0.5 ? v ref ** 0 0 0 1 0 0 0 0 xxxxx v in * < C0.5 ? v ref ** 0 0 0 0 1 1 1 1 11111 *the differential input voltage v in = in + C in C . **the differential reference voltage v ref = ref + C ref C . ** sub lsbs are below the 24-bit level. they may be included in averaging, or discarded without loss of resolution.
ltc2492 19 2492fb a new input word with en = 1 (the ? rst three bits are 101) and en2 = 1 is shifted into the device. rejection mode (fa, fb) the ltc2492 includes a high accuracy on-chip oscillator with no required external components. coupled with an integrated 4th order digital low pass ? lter, the ltc2492 rejects line frequency noise. in the default mode, the ltc2492 simultaneously rejects 50hz and 60hz by at least 87db. if more rejection is required, the ltc2492 can be con? gured to reject 50hz or 60hz to better than 110db. speed mode (spd) every conversion cycle, two conversions are combined to remove the offset (default mode). this result is free from offset and drift. in applications where the offset is not critical, the auto-calibration feature can be disabled with the bene? t of twice the output rate. while operating in the 2x mode (spd = 1), the linearity and full-scale errors are unchanged from the 1 mode performance. in both the 1 and 2 mode there is no latency. this enables input steps or multiplexer changes to settle in a single conversion cycle, easing system overhead and increasing the effective conversion rate. during temperature measurements, the 1 mode is always used independent of the value of spd. temperature sensor the ltc2492 includes an integrated temperature sensor. the temperature sensor is selected by setting im = 1. the digital output is proportional to the absolute temperature of the device. this feature allows the converter to perform cold junction compensation for external thermocouples or continuously remove the temperature effects of external sensors. the internal temperature sensor output is 28mv at 27c (300k), with a slope of 93.5v/c independent of v ref (see figures 4 and 5). slope calibration is not required if the reference voltage (v ref ) is known. a 5v reference has a slope of 314 lsbs 24 /c. the temperature is calculated applications information table 4. converter con? guration 1 0 en sgl odd a2 a1 a0 en2 im fa fb spd converter configuration 100xxxxxxxxxx k eep previous 101xxxxx0xxxx k eep previous 000xxxxxxxxxx k eep previous 101xxxxx10000 external input (see table 3) 50hz/60hz rejection, 1x 101xxxxx10010 external input (see table 3) 50hz rejection, 1x 101xxxxx10100 external input (see table 3) 60hz rejection, 1x 101xxxxx10001 external input (see table 3) 50hz/60hz rejection, 2x 101xxxxx10011 external input (see table 3) 50hz rejection, 2x 101xxxxx10101 external input (see table 3) 60hz rejection, 2x 101xxxxx1100x m easure temperature 50hz/60hz rejection, 1x 101xxxxx1101x m easure temperature 50hz rejection, 1x 101xxxxx1110x m easure temperature 60hz rejection, 1x 101xxxxx1x11x r eserved, do not use
ltc2492 20 2492fb applications information figure 4. internal ptat digital output vs temperature from the output code (dataout 24 ) for a 5v reference using the following formula: t k = dataout 24 /314 in kelvin if a different value of v ref is used, the temperature output is: t k = dataout 24 ? v ref /1570 in kelvin if the value of v ref is not known, the slope is determined by measuring the temperature sensor at a known temperature t n (in k) and using the following formula: slope = dataout 24 /t n this value of slope can be used to calculate further temperature readings using: t k = dataout 24 /slope all kelvin temperature readings can be converted to t c (c) using the fundamental equation: t c = t k C 273 serial interface timing modes the ltc2492s 4-wire interface is spi and microwire compatible. this interface offers several ? exible modes of operation. these include internal/external serial clock, 3- or 4-wire i/o, single cycle or continuous conversion. the following sections describe each of these timing modes in detail. in all cases, the converter can use the internal oscillator (f o = low) or an external oscillator connected to the f o pin. for each mode, the operating cycle, data input format, data output format, and performance remain the same. refer to table 5 for a summary. figure 5. absolute temperature error table 5. serial interface timing modes configuration sck source conversion cycle control data output control connection and waveforms external sck, single cycle conversion external cs and sck cs and sck figures 6, 7 external sck, 3-wire i/o external sck sck figure 8 internal sck, single cycle conversion internal cs cs figures 9, 10 internal sck, 3-wire i/o, continuous conversion internal continuous internal figure 11 temperature (k) 0 dataout 24 60000 80000 100000 120000 140000 400 2492 f04 40000 0 300 200 100 20000 v cc = 5v v ref = 5v slope = 314 lsb 24 /k temperature (c) C55 C30 C5 absolute error (c) 5 4 3 2 1 C4 C3 C2 C1 0 120 95 70 45 20 2492 f05 C5
ltc2492 21 2492fb external serial clock, single cycle operation this timing mode uses an external serial clock to shift out the conversion result and cs to monitor and control the state of the conversion cycle (see figure 6). the external serial clock mode is selected during the power- up sequence and on each falling edge of cs . in order to enter and remain in the external sck mode of operation, sck must be driven low both at power up and on each cs falling edge. if sck is high on the falling edge of cs the device will switch to the internal sck mode. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. while cs is low, eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the conversion is complete and the device is in the sleep state. independent of cs , the device automatically enters the sleep state once the conversion is complete; however, in order to reduce the power, cs must be high. when the device is in the sleep state, its conversion result is held in an internal static shift register. the device remains in the sleep state until the ? rst rising edge of sck is seen while cs is low. the input data is then shifted in via the sdi pin on each rising edge of sck (including the ? rst rising edge). the channel selection and converter con? guration mode will be used for the following conversion cycle. if the input channel or converter con? guration is changed during this i/o cycle, the new settings take effect on the conversion cycle following the data input/output cycle. the output data is shifted out the sdo pin on each falling edge of sck. this enables external circuitry to latch the output on the rising edge of sck. eoc can be latched on the ? rst rising edge of sck and the last bit of the conversion result can be latched on the 32nd rising edge of sck. on the 32nd falling edge of sck, the device begins a new conversion and sdo goes high ( eoc = 1) indicating a conversion is in progress. at the conclusion of the data cycle, cs may remain low and eoc monitored as an end-of-conversion interrupt. applications information figure 6. external serial clock, single cycle operation hi-z 2492 f06 cs sck (external) sdi sdo conversion sleep data input/output conversion v cc f o ref + ref C ch0 ch1 ch2 ch3 com sck sdi cs sdo gnd 12 1 13 14 8 9 10 11 7 3 4 6 5 2 reference voltage 0.1v to v cc analog inputs = external oscillator = internal oscillator ltc2492 2.7v to 5.5v 0.1f 10f 4-wire spi interface eoc bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 29 bit 30 bit 31 bit 18 bit 17 bit 0 1234567891011121314 32 1 0 en sgl a2 a1 a0 en2 im fa fb spd odd don't care don't care msb sig 0
ltc2492 22 2492fb hi-z 2492 f07 cs sck (external) sdi sdo conversion sleep data input/output sleep conversion v cc f o sck sdi gnd 6 reference voltage 0.1v to v cc analog inputs = external oscillator = internal oscillator ltc2492 4-wire spi interface eoc bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 29 bit 30 bit 31 12345678 1 0 en sgl a2 a1 a0 odd don't care don't care msb sig 0 ref + ref C ch0 ch1 ch2 ch3 com cs sdo 12 1 13 14 8 9 10 11 7 3 4 5 2 2.7v to 5.5v 0.1f 10f applications information typically, cs remains low during the data output/input state. however, the data output state may be aborted by pulling cs high any time between the 1st falling edge and the 32nd falling edge of sck (see figure 7). on the rising edge of cs , the device aborts the data output state and immediately initiates a new conversion. in order to program a new input channel, 8 sck clock pulses are required. if the data output sequence is aborted prior to the 8th falling edge of sck, the new input data is ignored and the previously selected input channel remains valid. if the rising edge of cs occurs after the 8th falling edge of sck, the new input channel is loaded and valid for the next conversion cycle. if cs goes high between the 8th falling edge and the 16th falling edge of sck, the new channel is still loaded, but the converter con? guration remains unchanged. in order to program both the input channel and converter con? guration, cs must go high after the 16th falling edge of sck (at this point all data has been shifted into the device). external serial clock, 3-wire i/o this timing mode uses a 3-wire serial i/o interface. the conversion result is shifted out of the device by an externally generated serial clock (sck) signal (see figure 8). cs is permanently tied to ground, simplifying the user interface or isolation barrier. the external serial clock mode is selected at the end of the power-on reset (por) cycle. the por cycle typically concludes 4ms after v cc exceeds 2v. the level applied to sck at this time determines if sck is internally generated or externally applied. in order to enter the external sck mode, sck must be driven low prior to the end of the por cycle. since cs is tied low, the end-of-conversion ( eoc ) can be continuously monitored at the sdo pin during the convert and sleep states. eoc may be used as an interrupt to an external controller. eoc = 1 while the conversion is in progress and eoc = 0 once the conversion is complete. figure 7. external serial clock, reduced output data length and valid channel selection
ltc2492 23 2492fb v cc f o sck sdi gnd reference voltage 0.1v to v cc analog inputs = external oscillator = internal oscillator ltc2492 3-wire spi interface eoc cs sck (external) sdi sdo 2492 f08 conversion sleep data input/output bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 29 bit 30 bit 31 1 0 en sgl a2 a1 a0 en2 im fa fb spd odd bit 18 bit 17 bit 0 1234567891011121314 32 don't care don't care msb sig 0 ref + ref C ch0 ch1 ch2 ch3 com sdo 12 1 13 14 8 9 10 11 7 3 5 6 4 2 2.7v to 5.5v 0.1f 10f cs conversion applications information figure 8. external serial clock, 3-wire operation ( ` c ` s = 0) on the falling edge of eoc , the conversion result is loading into an internal static shift register. the output data can now be shifted out the sdo pin under control of the externally applied sck signal. data is updated on the falling edge of sck. the input data is shifted into the device through the sdi pin on the rising edge of sck. on the 32nd falling edge of sck, sdo goes high, indicating a new conversion has begun. this data now serves as eoc for the next conversion. internal serial clock, single cycle operation this timing mode uses the internal serial clock to shift out the conversion result and cs to monitor and control the state of the conversion cycle (see figure 9). in order to select the internal serial clock timing mode, the serial clock pin (sck) must be ? oating or pulled high before the conclusion of the por cycle and prior to each falling edge of cs . an internal weak pull-up resistor is active on the sck pin during the falling edge of cs ; therefore, the internal sck mode is automatically selected if sck is not externally driven. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. once cs is pulled low, sck goes low and eoc is output to the sdo pin. eoc = 1 while the conversion is in progress and eoc = 0 if the device is in the sleep state. when testing eoc , if the conversion is complete ( eoc = 0), the device will exit sleep state. in order to return to the sleep state and reduce the power consumption, cs must be pulled high before the device pulls sck high. when the device is using its own internal oscillator (f o is tied low), the ? rst rising edge of sck occurs 12s (t eoctest = 12s) after the falling edge of cs . if f o is driven by an external oscillator of frequency f eosc , then t eoctest = 3.6/f eosc . if cs remains low longer than t eoctest , the ? rst rising edge of sck will occur and the conversion result is shifted out the sdo pin on the falling edge of sck. the serial input word (sdi) is shifted into the device on the rising edge of sck. after the 32nd rising edge of sck a new conversion automatically begins. sdo goes high ( eoc = 1) and sck
ltc2492 24 2492fb applications information remains high for the duration of the conversion cycle. once the conversion is complete, the cycle repeats. typically, cs remains low during the data output state. however, the data output state may be aborted by pulling cs high any time between the 1st rising edge and the 32nd falling edge of sck (see figure 10). on the rising edge of cs , the device aborts the data output state and immediately initiates a new conversion. in order to program a new input channel, 8 sck clock pulses are required. if the data output sequence is aborted prior to the 8th falling edge of sck, the new input data is ignored and the previously selected input channel remains valid. if the rising edge of cs occurs after the 8th falling edge of sck, the new input channel is loaded and valid for the next conversion cycle. if cs goes high between the 8th falling edge and the 16th falling edge of sck, the new channel is still loaded, but the converter con? guration remains unchanged. in order to program both the input channel and converter con? guration, cs must go high after the 16th falling edge of sck (at this point all data has been shifted into the device). internal serial clock, 3-wire i/o, continuous conversion. this timing mode uses a 3-wire interface. the conversion result is shifted out of the device by an internally generated serial clock (sck) signal (see figure 11). in this case, cs is permanently tied to ground, simplifying the user interface or transmission over an isolation barrier. the internal serial clock mode is selected at the end of the power-on reset (por) cycle. the por cycle is concluded approximately 4ms after v cc exceeds 2v. an internal weak pull-up is active during the por cycle; therefore, the internal serial clock timing mode is automatically selected if sck is ? oating or driven high. during the conversion, the sck and the serial data output pin (sdo) are high ( eoc = 1). once the conversion is complete, sck and sdo go low ( eoc = 0) indicating the conversion has ? nished and the device has entered the sleep state. the device remains in the sleep state a minimum amount of time (1/2 the internal sck period) then immediately begins outputting and inputting data. figure 9. internal serial clock, single cycle operation hi-z 2492 f09 cs sck (internal) sdi sdo conversion sleep data input/output v cc f o sck sdi gnd reference voltage 0.1v to v cc analog inputs = external oscillator = internal oscillator ltc2492 4-wire spi interface eoc bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 29 bit 30 bit 31 bit 18 bit 17 bit 0 1234567891011121314 32 1 0 en sgl a2 a1 a0 en2 im fa fb spd odd don't care don't care msb sig 0 optional 10k v cc ltc2492 25 2492fb applications information figure 10. internal serial clock, reduced data output length with valid channel and con? guration selection figure 11. internal serial clock, continuous operation eoc cs sck (internal) sdi sdo 2492 f11 conversion data input/output bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 29 bit 30 bit 31 1 0 en sgl a2 a1 a0 en2 im fa fb spd odd bit 18 bit 17 bit 0 23 14567891011121314 32 don't care don't care msb sig 0 v cc f o sck sdi sdo cs gnd reference voltage 0.1v to v cc analog inputs = external oscillator = internal oscillator ltc2492 3-wire spi interface optional 10k v cc ref + ref C ch0 ch1 ch2 ch3 com 12 1 13 14 8 9 10 11 7 3 5 6 4 2 2.7v to 5.5v 0.1f 10f conversion hi-z 2492 f10 cs sck (internal) sdi sdo conversion sleep data input/output v cc f o sck sdi gnd reference voltage 0.1v to v cc analog inputs = external oscillator = internal oscillator ltc2492 4-wire spi interface eoc bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 29 bit 30 bit 31 bit 18 bit17 bit 19 bit 19 1 2 3 4 5 6 7 8 9 10111213141516 1 0 en sgl a2 a1 a0 en2 im fa fb spd odd don't care don't care msb sig 0 optional 10k v cc ltc2492 26 2492fb the input data is shifted through the sdi pin on the rising edge of sck (including the ? rst rising edge) and the output data is shifted out the sdo pin on the falling edge of sck. the data input/output cycle is concluded and a new conversion automatically begins after the 32nd rising edge of sck. during the next conversion, sck and sdo remain high until the conversion is complete. the use of a 10k pull-up on sck for internal sck selection if cs is pulled high while the converter is driving sck low, the internal pull-up is not available to restore sck to a logic high state if sck is ? oating. this will cause the device to exit the internal sck mode on the next falling edge of cs . this can be avoided by adding an external 10k pull-up resistor to the sck pin. whenever sck is low, the ltc2492s internal pull-up at sck is disabled. normally, sck is not externally driven if the device is operating in the internal sck timing mode. however, certain applications may require an external driver on sck. if the driver goes hi-z after outputting a low signal, the internal pull-up is disabled. an external 10k pull-up resistor prevents the device from exiting the internal sck mode under this condition. a similar situation may occur during the sleep state when cs is pulsed high-low-high in order to test the conversion status. if the device is in the sleep state ( eoc = 0), sck will go low. if cs goes high before the time t eoctest , the internal pull-up is activated. if sck is heavily loaded, the internal pull-up may not restore sck to a high state before the next falling edge of cs . the external 10k pull-up resistor prevents the device from exiting the internal sck mode under this condition. preserving the converter accuracy the ltc2492 is designed to reduce as much as possible sensitivity to device decoupling, pcb layout, anti-aliasing circuits, line frequency perturbations, and temperature sensitivity. in order to achieve maximum performance a few simple precautions should be observed. digital signal levels the ltc2492s digital interface is easy to use. its digital inputs sdi, f o , cs , and sck (in external serial clock mode) accept standard cmos logic levels. internal hysteresis circuits can tolerate edge transition times as slow as 100s. the digital input signal range is 0.5v to v cc C 0.5v. during transitions, the cmos input circuits draw dynamic current. for optimal performance, application of signals to the serial data interface should be reserved for the sleep and data output periods. during the conversion period, overshoot and undershoot of fast digital signals applied to both the serial digital interface and the external oscillator pin (f o ) may degrade the converter performance. undershoot and overshoot occur due to impedance mismatch of the circuit board trace at the converter pin when the transition time of an external control signal is less than twice the propagation delay from the driver to the input pin. for reference, on a regular fr-4 board, the propagation delay is approximately 183ps/inch. in order to prevent overshoot, a driver with a 1ns transition time must be connected to the converter through a trace shorter than 2.5 inches. this becomes dif? cult when shared control lines are used and multiple re? ections occur. parallel termination near the input pin of the ltc2492 will eliminate this problem, but will increase the driver power dissipation. a series resistor from 27 to 54 (depending on the trace impedance and connection) placed near the driver will also eliminate over/under shoot without additional driver power dissipation. for many applications, the serial interface pins (sck, sdi, cs , f o ) remain static during the conversion cycle and no degradation occurs. on the other hand, if an external oscillator is used (f o driven externally) it is active during the conversion cycle. moreover, the digital ? lter rejection is minimal at the clock rate applied to f o . care must be taken to ensure external inputs and reference lines do not cross this signal or run near it. these issues are avoided when using the internal oscillator. applications information
ltc2492 27 2492fb applications information driving the input and reference the input and reference pins of the ltc2492 are connected directly to a switched capacitor network. depending on the relationship between the differential input voltage and the differential reference voltage, these capacitors are switched between these four pins. each time a capacitor is switched between two of these pins, a small amount of charge is transferred. a simpli? ed equivalent circuit is shown in figure 12. when using the ltc2492s internal oscillator, the input capacitor array is switched at 123khz. the effect of the charge transfer depends on the circuitry driving the input/ reference pins. if the total external rc time constant is less than 580ns the errors introduced by the sampling process are negligible since complete settling occurs. typically, the reference inputs are driven from a low impedance source. in this case, complete settling occurs even with large external bypass capacitors. the inputs (ch0 to ch3, com), on the other hand, are typically driven from larger source resistances. source resistances up to 10k may interface directly to the ltc2492 and settle completely; however, the addition of external capacitors at the input terminals in order to ? lter unwanted noise (anti-aliasing) results in incomplete settling. automatic differential input current cancellation in applications where the sensor output impedance is low (up to 10k with no external bypass capacitor or up to 500 with 0.001f bypass), complete settling of the input occurs. in this case, no errors are introduced and direct digitization is possible. for many applications, the sensor output impedance combined with external input bypass capacitors produces rc time constants much greater than the 580ns required for 1ppm accuracy. for example, a 10k bridge driving a 0.1f capacitor has a time constant an order of magnitude greater than the required maximum. the ltc2492 uses a proprietary switching algorithm that forces the average differential input current to zero independent of external settling errors. this allows direct digitization of high impedance sensors without the need of buffers. the switching algorithm forces the average input current on the positive input (i in + ) to be equal to the average input current on the negative input (i in C ). over the complete figure 12. ltc2492 equivalent analog input circuit in + in C 10k internal switch network 10k c eq 12pf 10k i in C ref + i ref + i in + i ref C 2492 f12 switching frequency f sw = 123khz internal oscillator f sw = 0.4 ? f eosc external oscillator ref C 10k 100 input multiplexer 100 iin iin vv r avg avg in cm ref cm eq + () = () = ? ? C () () . 05 i iref vv v r avg ref ref cm in cm + () + () 15 05 .C .? () () e eq in ref eq ref ref cm v vr where v ref ref v C ? : ( 2 =? +? ) ) C , = ? ? ? ? ? ? ? ? =? +? +? + ref ref v in in where in an in 2 d d in are the selected input channels v in in cm ? + = () C C . in r m internal oscillator eq ? ? ? ? ? ? ? ? ? = 2 271 6 0 0hz mode r 2.9 8 m internal oscillator 50hz/60 eq = h hz mode r0. 8 33 10 /f external oscil eq 12 eosc =? () l lator
ltc2492 28 2492fb applications information conversion cycle, the average differential input current (i in + C i in C ) is zero. while the differential input current is zero, the common mode input current (i in + + i in C )/2 is proportional to the difference between the common mode input voltage (v in(cm) ) and the common mode reference voltage (v ref(cm) ). in applications where the input common mode voltage is equal to the reference common mode voltage, as in the case of a balanced bridge, both the differential and common mode input currents are zero. the accuracy of the converter is not compromised by settling errors. in applications where the input common mode voltage is constant but different from the reference common mode voltage, the differential input current remains zero while the common mode input current is proportional to the difference between v in(cm) and v ref(cm) . for a reference common mode voltage of 2.5v and an input common mode of 1.5v, the common mode input current is approximately 0.74a. this common mode input current does not degrade the accuracy if the source impedances tied to in + and in C are matched. mismatches in source impedance lead to a ? xed offset error but do not effect the linearity or full scale reading. a 1% mismatch in a 1k source resistance leads to a 74v shift in offset voltage. in applications where the common mode input voltage varies as a function of the input signal level (single-ended type sensors), the common mode input current varies proportionally with input voltage. for the case of balanced input impedances, the common mode input current effects are rejected by the large cmrr of the ltc2492, leading to little degradation in accuracy. mismatches in source impedances lead to gain errors proportional to the difference between the common mode input and common mode reference. 1% mismatches in 1k source resistances lead to gain errors on the order of 15ppm. based on the stability of the internal sampling capacitors and the accuracy of the internal oscillator, a one-time calibration will remove this error. in addition to the input sampling current, the input esd protection diodes have a temperature dependent leakage current. this current, nominally 1na (10na max), results in a small offset shift. a 1k source resistance will create a 1v typical and a 10v maximum offset voltage. reference current similar to the analog inputs, the ltc2492 samples the differential reference pins (ref + and ref C ) transferring small amounts of charge to and from these pins, thus producing a dynamic reference current. if incomplete settling occurs (as a function the reference source resistance and reference bypass capacitance) linearity and gain errors are introduced. for relatively small values of external reference capacitance (c ref < 1nf), the voltage on the sampling capacitor settles for reference impedances of many k (if c ref = 100pf up to 10k will not degrade the performance) (see figures 13 and 14). figure 13. +fs error vs r source at v ref (small c ref ) figure 14. Cfs error vs r source at v ref (small c ref ) r source ( ) 0 +fs error (ppm) 50 70 90 10k 2492 f13 30 10 40 60 80 20 0 C10 10 100 1k 100k v cc = 5v v ref = 5v v in + = 3.75v v in C = 1.25v f o = gnd t a = 25c c ref = 0.01f c ref = 0.001f c ref = 100pf c ref = 0pf r source ( ) 0 Cfs error (ppm) C30 C10 10 10k 2492 f14 C50 C70 C40 C20 0 C60 C80 C90 10 100 1k 100 k v cc = 5v v ref = 5v v in + = 1.25v v in C = 3.75v f o = gnd t a = 25c c ref = 0.01f c ref = 0.001f c ref = 100pf c ref = 0pf
ltc2492 29 2492fb applications information in cases where large bypass capacitors are required on the reference inputs (c ref > 0.01f) full-scale and linearity errors are proportional to the value of the reference resistance. every ohm of reference resistance produces a full-scale error of approximately 0.5ppm (while operating in simultaneous 50hz/60hz mode) (see figures 15 and 16). if the input common mode voltage is equal to the reference common mode voltage, a linearity error of approximately 0.67ppm per 100 of reference resistance results (see figure 17). in applications where the input and reference r source ( ) 0 +fs error (ppm) 300 400 500 800 2492 f15 200 100 0 200 400 600 1000 v cc = 5v v ref = 5v v in + = 3.75v v in C = 1.25v f o = gnd t a = 25c c ref = 1 f, 10 f c ref = 0.1 f c ref = 0.01 f r source ( ) 0 Cfs error (ppm) C200 C100 0 800 2492 f16 C300 C400 C500 200 400 600 1000 v cc = 5v v ref = 5v v in + = 1.25v v in C = 3.75v f o = gnd t a = 25c c ref = 1 f, 10 f c ref = 0.1 f c ref = 0.01 f figure 15. +fs error vs r source at v ref (large c ref ) figure 16. Cfs error vs r source at v ref (large c ref ) v in /v ref C 0.5 inl (ppm of v ref ) 2 6 10 0.3 2492 f17 C2 C6 0 4 8 C4 C8 C10 C 0.3 C 0.1 0.1 0.5 v cc = 5v v ref = 5v v in(cm) = 2.5v t a = 25c c ref = 10f r = 1k r = 100 r = 500 figure 17. inl vs differential input voltage and reference source resistance for c ref > 1f common mode voltages are different, the errors increase. a 1v difference in between common mode input and common mode reference results in a 6.7ppm inl error for every 100 of reference resistance. in addition to the reference sampling charge, the reference esd protection diodes have a temperature dependent leakage current. this leakage current, nominally 1na (10na max) results in a small gain error. a 100 reference resistance will create a 0.5v full scale error. normal mode rejection and anti-aliasing one of the advantages delta-sigma adcs offer over conventional adcs is on-chip digital ? ltering. combined with a large oversample ratio, the ltc2492 signi? cantly simpli? es anti-aliasing ? lter requirements. additionally, the input current cancellation feature allows external low pass ? ltering without degrading the dc performance of the device.
ltc2492 30 2492fb applications information the sinc 4 digital ? lter provides excellent normal mode rejection at all frequencies except dc and integer multiples of the modulator sampling frequency (f s ) (see figures 18 and 19). the modulator sampling frequency is f s = 15,360hz while operating with its internal oscillator and f s = f eosc /20 when operating with an external oscillator of frequency f eosc . when using the internal oscillator, the ltc2492 is designed to reject line frequencies. as shown in figure 20, rejection nulls occur at multiples of frequency f n , where f n is differential input signal frequency (hz) 0f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s 9f s 10f s 11f s 12f s input normal mode rejection (db) 2492 f18 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 figure 18. input normal mode rejection, internal oscillator and 50hz rejection mode differential input signal frequency (hz) 0f s input normal mode rejection (db) 2492 f19 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 2f s 3f s 4f s 5f s 6f s 7f s 8f s 9f s 10f s figure 19. input normal mode rejection, internal oscillator and 60hz rejection mode input signal frequency (hz) input normal mode rejection (db) 2492 f20 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 f n 0 2f n 3f n 4f n 5f n 6f n 7f n 8f n f n = f eosc/5120 figure 20. input normal mode rejection at dc input signal frequency (hz) 250f n 252f n 254f n 256f n 258f n 260f n 262f n input normal mode rejection (db) 2492 f21 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 figure 21. input normal mode rejection at f s = 256 ? f n determined by the input control bits fa and fb (f n = 50hz or 60hz or 55hz for simultaneous rejection). multiples of the modulator sampling rate (f s = f n ? 256) only reject noise to 15db (see figure 21); if noise sources are present at these frequencies anti-aliasing will reduce their effects. the user can expect to achieve this level of performance using the internal oscillator, as shown in figures 22, 23, and 24. measured values of normal mode rejection are shown superimposed over the theoretical values in all three rejection modes.
ltc2492 31 2492fb figure 22. input normal mode rejection vs input frequency with input perturbation of 100% (60hz notch) applications information traditional high order delta-sigma modulators suffer from potential instabilities at large input signal levels. the proprietary architecture used for the ltc2492 third order modulator resolves this problem and guarantees stability with input signals 150% of full-scale. in many industrial applications, it is not uncommon to have microvolt level signals superimposed over unwanted error sources with several volts of peak-to-peak noise. figures 25 and 26 show measurement results for the rejection of a 7.5v peak-to-peak noise source (150% of full scale) applied to the ltc2492. from these curves, it is shown that the rejection performance is maintained even in extremely noisy environments. input frequency (hz) 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 normal mode rejection (db) 2492 f22 0 C20 C40 C60 C80 C100 C120 v cc = 5v v ref = 5v v in(cm) = 2.5v v in(p-p) = 5v t a = 25c measured data calculated data input frequency (hz) 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 normal mode rejection (db) 2492 f23 0 C20 C40 C60 C80 C100 C120 v cc = 5v v ref = 5v v in(cm) = 2.5v v in(p-p) = 5v t a = 25c measured data calculated data figure 23. input normal mode rejection vs input frequency with input perturbation of 100% (50hz notch) input frequency (hz) 0 20 40 60 80 100 120 140 160 180 200 220 normal mode rejection (db) 2492 f24 0 C20 C40 C60 C80 C100 C120 v cc = 5v v ref = 5v v in(cm) = 2.5v v in(p-p) = 5v t a = 25c measured data calculated data figure 24. input normal mode rejection vs input frequency with input perturbation of 100% (50hz/60hz notch) input frequency (hz) 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 normal mode rejection (db) 2492 f25 0 C20 C40 C60 C80 C100 C120 v cc = 5v v ref = 5v v in(cm) = 2.5v t a = 25c v in(p-p) = 5v v in(p-p) = 7.5v (150% of full scale) figure 25. measure input normal mode rejection vs input frequency with input perturbation of 150% (60hz notch) input frequency (hz) 0 normal mode rejection (db) 2492 f26 0 C20 C40 C60 C80 C100 C120 v cc = 5v v ref = 5v v in(cm) = 2.5v t a = 25c v in(p-p) = 5v v in(p-p) = 7.5v (150% of full scale) 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 figure 26. measure input normal mode rejection vs input frequency with input perturbation of 150% (50hz notch)
ltc2492 32 2492fb applications information using the 2x speed mode of the ltc2492 alters the rejection characteristics around dc and multiples of f s . the device bypasses the offset calibration in order to increase the output rate. the resulting rejection plots are shown in figures 27 and 28. 1x type frequency rejection can be achieved using the 2x mode by performing a running average of the conversion results (see figure 29). output data rate when using its internal oscillator, the ltc2492 produces up to 7.5 samples per second (sps) with a notch frequency of 60hz. the actual output data rate depends upon the length of the sleep and data output cycles which are controlled by the user and can be made insigni? cantly short. when operating with an external conversion clock (f o connected to an external oscillator), the ltc2492 output data rate can be increased. the duration of the conversion cycle is 41036/f eosc . if f eosc = 307.2khz, the converter behaves as if the internal oscillator is used. an increase in f eosc over the nominal 307.2khz will translate into a proportional increase in the maximum output data rate (up to a maximum of 100sps). the increase in output rate leads to degradation in offset, full-scale error, and effective resolution as well as a shift in frequency rejection. when using the integrated temperature sensor, the internal oscillator should be used or an external oscillator, f eosc = 307.2khz maximum. a change in f eosc results in a proportional change in the internal notch position. this leads to reduced differential mode rejection of line frequencies. the common mode rejection of line frequencies remains unchanged, thus fully differential input signals with a high degree of symmetry on both the in + and in C pins will continue to reject line frequency noise. an increase in f eosc also increases the effective dynamic input and reference current. external rc networks will continue to have zero differential input current, but the time required for complete settling (580ns for f eosc = 307.2khz) is reduced, proportionally. once the external oscillator frequency is increased above 1mhz (a more than 3x increase in output rate) the effectiveness of internal auto calibration circuits begins to degrade. this results in larger offset errors, full scale errors, and decreased resolution (see figures 30 to 37). input signal frequency (f n ) input normal rejection (db) 2492 f27 0 C20 C40 C60 C80 C100 C120 0 f n 2f n 3f n 4f n 5f n 6f n 7f n 8f n figure 27. input normal mode rejection 2x speed mode input signal frequency (f n ) input normal rejection (db) 2492 f28 0 C20 C40 C60 C80 C100 C120 250 248 252 254 256 258 260 262 264 figure 28. input normal mode rejection 2x speed mode
ltc2492 33 2492fb differential input signal frequency (hz) 48 C70 C80 C90 C100 C110 C120 C130 C140 54 58 2492 f29 50 52 56 60 62 normal mode rejection (db) no average with running average output data rate (readings/sec) C10 offset error (ppm of v ref ) 10 30 50 0 20 40 20 40 60 80 2492 f30 10 0 10 030507090 v in(cm) = v ref(cm) v cc = v ref = 5v v in = 0v f o = ext clock t a = 85c t a = 25c output data rate (readings/sec) 0 C3500 Cfs error (ppm of v ref ) C3000 C2000 C1500 C1000 0 10 50 70 2492 f32 C2500 C500 40 90 100 20 30 60 80 v in(cm) = v ref(cm) v cc = v ref = 5v f o = ext clock t a = 85c t a = 25c output data rate (readings/sec) 0 0 +fs error (ppm of v ref ) 500 1500 2000 2500 3500 10 50 70 2492 f31 1000 3000 40 90 100 20 30 60 80 v in(cm) = v ref(cm) v cc = v ref = 5v f o = ext clock t a = 85c t a = 25c output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 20 24 10 50 70 2492 f33 14 22 40 90 100 20 30 60 80 v in(cm) = v ref(cm) v cc = v ref = 5v v in = 0v f o = ext clock res = log 2 (v ref /noise rms ) t a = 85c t a = 25c output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 22 10 50 70 2492 f34 14 20 40 90 100 20 30 60 80 t a = 85c t a = 25c v in(cm) = v ref(cm) v cc = v ref = 5v f o = ext clock res = log 2 (v ref /inl max ) applications information figure 29. input normal mode rejection 2x speed mode with and without running averaging figure 30. offset error vs output data rate and temperature figure 31. +fs error vs output data rate and temperature figure 32.Cfs error vs output data rate and temperature figure 33. resolution (noise rms 1lsb) vs output data rate and temperature figure 34. resolution (inl max 1lsb) vs output data rate and temperature figure 36. resolution (noise rms 1lsb) vs output data rate and reference voltage figure 37. resolution (inl max 1lsb) vs output data rate and reference voltage output data rate (readings/sec) 0 C10 offset error (ppm of v ref ) C5 5 10 20 10 50 70 2492 f35 0 15 40 90 100 20 30 60 80 v cc = 5v, v ref = 2.5v v cc = v ref = 5v v in(cm) = v ref(cm) v in = 0v f o = ext clock t a = 25c output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 20 24 10 50 70 2492 f36 14 22 40 90 100 20 30 60 80 v in(cm) = v ref(cm) v in = 0v f o = ext clock t a = 25c res = log 2 (v ref /noise rms ) v cc = 5v, v ref = 2.5v v cc = v ref = 5v output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 22 10 50 70 2492 f37 14 20 40 90 100 20 30 60 80 v cc = 5v, v ref = 2.5v v cc = v ref = 5v v in(cm) = v ref(cm) v in = 0v ref C = gnd f o = ext clock t a = 25c res = log 2 (v ref /inl max ) figure 35. offset error vs output data rate and reference voltage
ltc2492 34 2492fb applications information easy drive adcs simplify measurement of high impedance sensors delta-sigma adcs, with their high accuracy and high noise immunity, are ideal for directly measuring many types of sensors. nevertheless, input sampling currents can overwhelm high source impedances or low-bandwidth, micropower signal conditioning circuits. the ltc2492 solves this problem by balancing the input currents, thus simplifying or eliminating the need for signal conditioning circuits. a common application for a delta-sigma adc is thermistor measurement. figure 38 shows two examples of thermistor digitization bene? ting from the easy drive technology. the ? rst circuit (applied to input channels ch0 and ch1) uses balanced reference resistors in order to balance the common mode input/reference voltage and balance the differential input source resistance. if reference resistors r1 and r4 are exactly equal, the input current is zero and no errors result. if these resistors have a 1% tolerance, the maximum error in measured resistance is 1.6 due to a shift in common mode voltage; far less than the 1% error of the reference resistors themselves. no ampli? er is required, making this an ideal solution in micropower applications. easy drive also enables very low power, low bandwidth ampli? ers to drive the input to the ltc2492. as shown in figure 38, ch2 is driven by the lt1494. the lt1494 has excellent dc specs for an ampli? er with 1.5a supply current (the maximum offset voltage is 150v and the open loop gain is 100,000). its 2khz bandwidth makes it unsuitable for driving conventional delta sigma adcs. adding a 1k, 0.1f ? lter solves this problem by providing a charge reservoir that supplies the ltc2492 instantaneous current, while the 1k resistor isolates the capacitive load from the lt1494. conventional delta sigma adcs input sampling current lead to dc errors as a result of incomplete settling in the external rc network. the easy drive technology cancels the differential input current. by balancing the negative input (ch3) with a 1k, 0.1f network errors due to the common mode input current are cancelled.
ltc2492 35 2492fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description 3.00 0.10 (2 sides) 4.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wged-3) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom viewexposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 3.00 ref 1.70 0.05 1 7 14 8 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (de14) dfn 0806 rev b pin 1 notch r = 0.20 or 0.35 s 45 chamfer 3.00 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 package outline 0.25 0.05 0.25 0.05 0.50 bsc 3.30 0.05 3.30 0.10 0.50 bsc de package 14-lead plastic dfn (4mm 3mm) (reference ltc dwg 05-08-1708 rev a)
ltc2492 36 2492fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt 1008 rev b? printed in usa related parts part number description comments lt1236a-5 precision bandgap reference, 5v 0.05% max initial accuracy, 5ppm/c drift lt1460 micropower series reference 0.075% max initial accuracy, 10ppm/c max drift lt1790 micropower sot-23 low dropout reference family 0.05% max initial accuracy, 10ppm/c max drift ltc2400 24-bit, no latency ? adc in so-8 0.3ppm noise, 4ppm inl, 10ppm total unadjusted error, 200a ltc2410 24-bit, no latency ? adc with differential inputs 0.8v rms noise, 2ppm inl ltc2411/ ltc2411-1 24-bit, no latency ? adcs with differential inputs in msop 1.45v rms noise, 4ppm inl, simultaneous 50hz/60hz rejection (ltc2411-1) ltc2413 24-bit, no latency ? adc with differential inputs simultaneous 50hz/60hz rejection, 800nv rms noise ltc2440 high speed, low noise 24-bit ? adc 3.5khz output rate, 200nv noise, 24.6 enobs ltc2442 24-bit, high speed 2-channel and 4-channel ? adc with integrated ampli? er 8khz output rate, 220nv noise, simultaneous 50hz/60hz rejection ltc2449 24-bit, high speed 8-channel and 16-channel ? adc 8khz output rate, 200nv noise, simultaneous 50hz/60hz rejection ltc2480 16-bit ? adc with easy drive inputs, 600nv noise, programmable gain, and temperature sensor pin compatible with ltc2482/ltc2484 ltc2481 16-bit ? adc with easy drive inputs, 600nv noise, i 2 c interface, programmable gain, and temperature sensor pin compatible with ltc2483/ltc2485 ltc2482 16-bit ? adc with easy drive inputs pin compatible with ltc2480/ltc2484 ltc2483 16-bit ? adc with easy drive inputs, and i 2 c interface pin compatible with ltc2481/ltc2485 ltc2484 24-bit ? adc with easy drive inputs pin compatible with ltc2480/ltc2482 ltc2485 24-bit ? adc with easy drive inputs, i 2 c interface, and temperature sensor pin compatible with ltc2481/ltc2483 ltc2488 2-channel and 4-channel 16-bit ? adc with easy drive inputs pin compatible with ltc2492 ltc2496/ ltc2498 16-channel/8-channel 16-bit/24-bit ? adc with easy drive inputs, and spi interface timing compatible with ltc2492 typical application figure 38. easy drive adcs simplify measurement of high impedance sensors v cc f o sck sdi gnd = external oscillator = internal oscillator ltc2492 3-wire spi interface 2492 f38 sdo 12 1 ref + 13 ref C 14 ch0 8 ch1 9 ch2 10 ch3 11 com 7 3 5 6 4 2 5v 0.1f 10f cs 5v i in + = 0 i in C = 0 r1 51.1k r4 51.1k c4 0.1 f c3 0.1 f r3 10k to 100k C + 102k 5v 5v lt1494 0.1 f 0.1 f 0.1 f 1k 1k 10k to 100k

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